1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having respective areas for high-voltage and low-voltage transistors.
2. Discussion of the Related Art
Referring to FIG. 1, illustrating a semiconductor device according to a related art, a high-voltage transistor of about 30V or higher is arranged in a high-voltage transistor area and a low-voltage transistor is arranged in a low-voltage transistor area. A local oxidation of silicon (LOCOS) layer 111 is used as a device isolation layer for each of the high- and low-voltage transistors.
The high-voltage transistor includes n+ type source/drain regions 141 provided in predetermined upper parts of a p− type substrate 100 to be spaced apart from each other. In particular, the drain region 141 is arranged within an n− type extended drain area 103 working as a drift area. The substrate 100 between the n+ type source region 141 and the n− type extended drain area 103 corresponds to a channel area 101. A gate insulating layer pattern 121 and a gate conductive layer pattern 122 are sequentially stacked on the channel area 101. The n+ type source/drain regions 141 are electrically connected to source (S) and drain (D) electrodes, respectively.
The low-voltage transistor includes n+ type source/drain regions 151 provided in predetermined upper parts of the p− type substrate 100 to be spaced apart from each other. The substrate 100 between the n+ type source/drain regions 151 corresponds to a channel area 102. A gate insulating layer pattern 131 and a gate conductive layer pattern 132 are sequentially stacked on the channel area 102. The n+ source/drain regions 151 are electrically connected to source and drain electrodes, respectively.
In the above-configured semiconductor device according to the related art, the LOCOS layer 111 is used as a device isolation layer of the high-voltage transistor area to secure a high breakdown voltage for the high-voltage transistor. Since the LOCOS layer 111 is provided to the low-voltage transistor area, however, the chip area of the low-voltage transistor area is increased.
Referring to FIG. 2, illustrating another semiconductor device according to a related art, a high-voltage transistor of about 30V or higher is arranged in a high-voltage transistor area and a low-voltage transistor is arranged in a low-voltage transistor area. A shallow-trench isolation layer 211 is used as a device isolation layer for each of the high- and low-voltage transistors, to enable a smaller chip area. Yet, in the high-voltage transistor area, it is difficult for the shallow-trench isolation layer 211 to enable a required level of breakdown voltage. The on-resistance and leakage current characteristic are degraded due to a linear profile of the shallow-trench isolation layer 211.